The ability to dope polysilicon gates to different degrees allows one to adjust the work function of gate electrode materials to particular types of complementary metal oxide silicon (CMOS) transistors. It is desirable to adjust the work function of a gate electrode to be close to either the conduction band or the valence band of silicon, because this reduces the threshold voltage of the transistor, thereby facilitating a high drive current. For instance, dual work function gates are advantageously used in semiconductor devices having both PMOS and NMOS transistors. The use of doped polysilicon gates becomes problematic, however, as the dimensions of gates and gate insulators are reduced.
Polysilicon gates can only accommodate a finite amount of dopant. This limitation can result in a depletion of gate charge carriers at the interface between the gate and gate dielectric, when the gate electrode of a device is biased to invert the channel. Consequently, the electrical thickness of the gate dielectric is substantially increased, thereby deteriorating the performance characteristics of the transistor, such as reducing the drive current and switching speed. For instance, the electrical thickness of a gate dielectric in some PMOS transistors can increase from about 1.0 nanometer during accumulation mode, to about 1.8 nanometer during inversion mode.
Metal gates are an attractive alternative to polysilicon because they have a larger supply of charge carriers than doped polysilicon gates. When a metal gate is inverted, there is no substantial depletion of carriers at the interface between the metal gate and gate dielectric. Accordingly, the transistor's performance is not deteriorated because the electrical thickness of the gate stack is not increased. The integration of semiconductor transistors having dual work function metal gates has been troublesome, however.
Ideally, dual work function metal gates should be compatible with conventional gate dielectric materials and have suitably adjustable work functions. Moreover, the fabrication of metal gates should be easily adaptable to conventional semiconductor device fabrication processes. It has proven challenging, however, to simply deposit and etch metals to form gate structures. For instance, it can be difficult to find etchants and etch conditions where gate metals can be etched with high selectively, that is, without damaging the underlying gate insulator and silicon substrate. Additionally, if two different metals are used to provide dual work function gates, a deposit-and-etch fabrication scheme entails the further complications of selectively etching one gate metal over another gate metal, or etching both metal gates simultaneously.
Previous attempts to reduce these difficulties have not been entirely successful. For instance, to protect the gate dielectric when the metal layer is patterned and etched, some manufacturers have proposed depositing an etch barrier layer between the gate dielectric and the metal layers. This process not only adds to the thickness to the gate dielectric, but also involves additional processing steps. To avoid the need to selectively etch one metal over another metal, some have proposed using a single metal, having midrange work function, as the gate material. Unfortunately, transistors having such single-metal gate electrodes have undesirably high threshold voltages.
Others have proposed a gate-last fabrication scheme. First, a conventional transistor is fully manufactured, including the fabrication of a polysilicon gate and with underlying doped regions implanted. The polysilicon gate and underlying gate dielectric are then removed to provide a gate opening. A new gate dielectric is then conformally deposited on the sides and bottom of the gate opening, followed by filling the gate opening with a metal, to replace the polysilicon gate. In addition to having extra processing steps, such gate-last fabrication schemes have a number of limitations.
In a gate-last fabrication schemes, dopants are implanted into various components of the transistor, such as the source and drain, before the new gate dielectric and replacing metal gate is formed. It follows, therefore, that gate-last fabrication schemes require that all subsequent steps to depositing the gate metal and gate dielectric are done at low temperatures (e.g., below about 700° C.) to prevent the diffusion of dopants. Low temperature processing is undesirable because high temperature anneals are done to improve the quality of the gate dielectric.
In addition, transistors manufactured using gate-last fabrication schemes are more prone to fringe-induced barrier lowering (FIBL). As well known by those skilled in the art, FIBL involves increased coupling between the source and the gate electrode due to the presence of insulating material with a high dielectric constant on the sides of the gate opening. This, in turn, can cause barrier lowering, resulting in transistors with undesirably high leakage current.
There is also a problem with the alignment of source and drain structures when using a gate-last fabrication scheme. When the conventional transistor is manufactured, the polysilicon gate is used as a mask to allow precise definition of the source/drain regions and alignment with the polysilicon gate. Such self-aligned structures minimize overlap between the gate and source and drain and thereby advantageously improve transistor performance reducing the capacitance between the gate and source drain structure.
Self-alignment is lost, however, when the polysilicon gate is replaced by the metal gate in a replacement gate flow. The metal gate does not have the same dimensions as the polysilicon gate because procedures to remove polysilicon can also remove portions of gate sidewall material. The presence of gate insulating material on the sides of the gate opening also contributes to the replacing metal gate having a different size than the polysilicon gate.
Accordingly, what is needed in the art is a method of manufacturing semiconductor devices having dual work function metal electrodes, while not introducing additional problems into semiconductor device manufacturing processes.